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US 2025/0095722 A1Published application
Random access memory with metal bridges connecting adjacent read transistors
AssigneeUnited Microelectronics Corp.
InventorsMing-Hsiu Wu, Tsung-Hsun Wu
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Abstract
A random access memory, including a first gate crossing over a first doped region to constitute a write transistor, a second gate crossing over a second doped region to constitute a first read transistor, a third gate crossing over the first doped region and the second doped region to constitute a second read transistor, a metal bridge electrically connected to the second gate and the third gate, and a junction of the first source, the second gate and the third gate is a storage node.
Claims15
A random access memory, comprising:
- a substrate with a first doped region and a second doped region adjacent to each other in a first direction and extending in a second direction;
- a first gate extending in said first direction on said substrate and crossing over said first doped region, wherein said first doped regions at two sides of said first gate are a first drain and a first source, respectively, and said first gate, said first drain and said first source constitute a write transistor;
- a second gate extending in said first direction on said substrate and crossing over said second doped region, wherein said second doped regions at two sides of said second gate are a second drain and a common source, respectively, and said second gate, said second drain and said common source constitute a first read transistor;
- a third gate extending in said first direction on said substrate and crossing over said first doped region and said second doped region, wherein said second doped regions at two sides of said third gate are said common source and a third drain, respectively, and said first doped regions at one side of said third gate is said first source, and said third gate, said common source and said third drain constitute a second read transistor;
- and
- a metal bridge electrically connected to said second gate and said third gate;
- wherein a junction of said first source, said second gate and said third gate is a storage node.
4 more elements
Dependencies are inferred from the claim text.