Refresh control circuit and memory

A refresh control circuit, applied to a memory, and comprising a control circuit, a counter circuit, and an indication circuit;

• the control circuit being connected to an output terminal of the indication circuit, and being configured to:
• when a refresh management feature is disabled, output an all-bank normal refresh request or a same-bank normal refresh request according to a received address command signal if the indication circuit currently outputs an invalid indication signal, or output an all-bank refresh management refresh request or a same-bank refresh management refresh request according to a received address command signal if the indication circuit currently outputs a valid indication signal, and the same-bank refresh management refresh request being configured to indicate to perform a row hammer refresh;
• the counter circuit being connected to an output terminal of the control circuit, and being configured to count an accumulative quantity of same-bank normal refresh requests and same-bank refresh management refresh requests that are continuously output by the control circuit, output a counting result, and perform resetting and start counting again in response to the current counting result reaching a set upper limit value or when the control circuit outputs the all-bank normal refresh request or the all-bank refresh management refresh request;
• and
• the indication circuit being connected to an output terminal of the counter circuit, and being configured to output the valid indication signal if the current counting result is in a preset range, or output the invalid indication signal if the current counting result is not in a preset range.