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US 2025/0095709 A1Published application
Memory with row hammer mitigation technique
AssigneeSK hynix Inc.
InventorsWoongrae KIM, Hoiju CHUNG
Life of this patent
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Abstract
A memory includes: a memory core; a list storage circuit suitable for storing a weak row list of rows that are vulnerable to a row hammer attack in the memory core; and a row hammer attack detection circuit suitable for selecting rows that are row-hammer-attacked among rows in the memory core as hammered rows, and increasing a probability that the rows stored in the list storage circuit are selected as the hammered rows.
Claims4
A memory comprising:
- a memory core;
- a list storage circuit suitable for storing a weak row list of rows that are vulnerable to a row hammer attack in the memory core;
- a sampling circuit suitable for sampling and storing a portion of active addresses used for active operations of the memory core and increasing a sampling probability of an active address corresponding to the rows stored in the list storage circuit among the active addresses;
- and
- a selection circuit suitable for selecting one among the sampled addresses stored in the sampling circuit as a hammered row address in a predetermined order whenever a smart refresh operation is performed.
2 more elements
Dependencies are inferred from the claim text.