Memory device

A memory device comprising:

• a memory cell array that including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells respectively connected to one of the plurality of bit lines and one of the plurality of word lines, the memory cell array in which first to ninth areas are set;
• a first column switch circuit connected to the plurality of bit lines and provided on one end side in a first direction of the memory cell array;
• a second column switch circuit connected to the plurality of bit lines and provided on the other end side in the first direction of the memory cell array;
• a first row switch circuit connected to the plurality of word lines and provided on one end side in a second direction of the memory cell array;
• and
• a second row switch circuit connected to the plurality of word lines and provided on the other end side in the second direction of the memory cell array,
• wherein
• in a case where a memory cell in the first area is selected, the first and second column switch circuits and the first and second row switch circuits are activated, and
• in a case where a memory cell in the second area is selected, the first column switch circuit and the first row switch circuit are activated, and
• in a case where a memory cell in the third area is selected, the second column switch circuit and the first row switch circuit are activated, and
• in a case where a memory cell in the fourth area is selected, the second column switch circuit and the second row switch circuit are activated, and
• in a case where a memory cell in the fifth area is selected, the first column switch circuit and the second row switch circuit are activated, and
• in a case where a memory cell in the sixth area is selected, the first and second column switch circuits and the first row switch circuit are activated, and
• in a case where a memory cell in the seventh area is selected, the second column switch circuit and the first and second row switch circuits are activated, and
• in a case where a memory cell in the eighth area is selected, the first and second column switch circuits and the second row switch circuit are activated, and
• in a case where a memory cell in the ninth area is selected, the first column switch circuit and the first and second row switch circuits are activated.