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US 2025/0095698 A1Published application
High speed memory circuit architecture with improved area and power efficiency
AssigneeQUALCOMM Incorporated
InventorsSonia GHOSH, Xiao CHEN, Chi-Jui CHEN
Life of this patent
Estimating the term…
Abstract
A random-access memory has its bitcells arranged into a first pair of banks and a second pair of banks. The first pair of banks and second pair of banks are separated by a central controller that contains sense amplifiers and write drivers for the first pair of banks and for the second pair of banks.
Claims30
A memory comprising:
- a first bank of bitcells arranged into a first plurality of columns;
- a first plurality of read column multiplexers coupled to the first plurality of columns, the first plurality of read column multiplexers being located adjacent a first edge of the first bank of bitcells;
- a second bank of bitcells arranged into a second plurality of columns, wherein the first edge of the second bank of bitcells is positioned to face the first edge of the first bank of bitcells;
- a second plurality of read column multiplexers coupled to the second plurality of columns, the second plurality of read column multiplexers being located adjacent the first edge of the second bank of bitcells;
- a plurality of read circuits being located adjacent a second edge of the second bank of bitcells;
- and
- a first plurality of read bit lines coupled to the first plurality of read column multiplexers, the second plurality of read column multiplexers, and the plurality of sense amplifiers.
4 more elements
A method of reading from a memory, comprising:
- coupling a pair of local bit lines from a first selected column of bitcells from a first bank of bitcells through a first read column multiplexer to a first pair of read bit lines during a first read operation, wherein the first pair of read bit lines extend from the first read column multiplexer and across a second bank of bitcells to a first sense amplifier;
- sensing a first bit in the first sense amplifier during the first read operation;
- coupling a pair of local bit lines from a selected column of bitcells in the second bank of bitcells through a second read column multiplexer to the first pair of read bit lines during a second read operation, wherein the second read column multiplexer and the first read column multiplexer are both positioned between the first bank of bitcells and the second bank of bitcells;
- and
- sensing a second bit in the first sense amplifier during the second read operation.
2 more elements
A memory comprising:
- a first bank of bitcells arranged into a first plurality of columns;
- a first plurality of write column multiplexers coupled to the first plurality of columns, the first plurality of write column multiplexers being located adjacent a first edge of the first bank of bitcells;
- a second bank of bitcells arranged into a second plurality of columns, each column in the second plurality of columns extending from a first edge of the second bank of bitcells to a second edge of the second bank of bitcells, wherein the first edge of the second bank of bitcells faces the first edge of the first bank of bitcells;
- a second plurality of write column multiplexers coupled to the second plurality of columns, the second plurality of write column multiplexers being located adjacent the first edge of the second bank of bitcells;
- a plurality of write drivers positioned adjacent the second edge of the second bank of bitcells;
- and
- a first plurality of write bit lines coupled to the first plurality of write column multiplexers, the second plurality of write column multiplexers, and the plurality of write drivers.
4 more elements
A memory comprising:
- a first pair of banks;
- a second pair of banks;
- a sense amplifier located between the first pair of banks and the second pair of banks;
- a first read column multiplexer configured to couple a pair of local bit lines for an addressed column of bitcells from a first bank in the first pair of banks to a first pair of output nodes;
- a second read column multiplexer configured to couple a pair of local bit lines for an addressed column of bitcells from a second bank in the first pair of banks to the first pair of output nodes;
- and
- a first pair of read bit lines coupled between the first pair of output nodes and the sense amplifier.
4 more elements
Dependencies are inferred from the claim text.