Memory device and method of manufacturing the same

A memory device comprising:

• interlayer insulation layers and gate lines alternately stacked on each other between bit lines and source lines;
• plugs vertically passing through the interlayer insulation layers and the gate lines;
• and
• a first slit vertically passing through the interlayer insulation layers and the gate lines to separate the interlayer insulation layers and the gate lines into different memory blocks,
• wherein each of the gate lines includes:
• a barrier layer;
• a first conductive layer surrounded by the barrier layer;
• and
• a second conductive layer surrounded by the first conductive layer and having a grain size different from a grain size of the first conductive layer, wherein a size of the second conductive layer increases with decreasing distance of the second conductive layer from the first slit.

A method of manufacturing a memory device, the method comprising:

• alternately stacking interlayer insulation layers and sacrificial layers;
• forming plugs vertically passing through the interlayer insulation layers and the sacrificial layers;
• forming a slit vertically passing through the interlayer insulation layers and the sacrificial layers in a boundary area between different memory blocks;
• removing the sacrificial layers exposed through a sidewall of the slit;
• forming a first conductive layer in an area from which the sacrificial layers are removed;
• and
• filling a void generated when the first conductive layer is formed with a second conductive layer having a first grain size different from a grain size of the first conductive layer.