US 2025/0095693 A1 · CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LAYER

Abstract

An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits, which may include MOSFET transistors. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. The logic circuits may include word line drivers and sense amplifiers. Word lines in different memory layers may share the same word line driver. Bit lines in different memory layers may share the same sense amplifier. The IC device may include front-back word line drivers, near-far sense amplifiers, near-far word line drivers, or front-back sense amplifiers. A memory layer may be bonded with the CMOS layer through a bonding layer that provides a bonding interface between the memory layer and the CMOS layer.

Claims20

Dependent claims

An integrated circuit (IC) device, comprising:

a logic layer comprising a word line driver;
a first memory layer at a first side of the logic layer, the first memory layer comprising first memory cells and a first word line coupled to the first memory cells;
and
a second memory layer at a second side of the logic layer, the second memory layer comprising second memory cells and a second word line coupled to the second memory cells,
wherein the second side opposes the first side, and the first word line and the second word line are coupled to the word line driver.

2 more elements

An integrated circuit (IC) device, comprising:

a logic layer comprising a first sense amplifier and a second sense amplifier;
a first memory layer at a first side of the logic layer, the first memory layer comprising first memory cells and a first bit line coupled to the first memory cells;
a second memory layer at the first side of the logic layer, the second memory layer comprising second memory cells and a second bit line coupled to the second memory cells;
and
a third memory layer at a second side of the logic layer, the third memory layer comprising third memory cells and a third bit line coupled to the third memory cells,
wherein the first memory layer is between the second memory layer and the logic layer, the second side opposes the first side, the first bit line and the third bit line are coupled to the first sense amplifier, and the second bit line are coupled to the second sense amplifier that is separate from the first sense amplifier.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/467,947Filed 15 Sep 2023

Published

20 Mar 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 5/063
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C 11/4091
Read-write [R-W] circuits: sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or…
G11C 11/419
For memory cells of the field-effect type: read-write [R-W] circuits

Connections of bit lines and word lines in stacked memory layers to a complementary metal-oxide-semiconductor layer

Life of this patent

Connections of bit lines and word lines in stacked memory layers to a complementary metal-oxide-semiconductor layer

Life of this patent

Abstract

Claims20