US 2025/0095692 A1Published application

Semiconductor memory device

AssigneeKioxia Corporation

InventorsTakafumi MASUDA, Mutsumi OKAJIMA, Nobuyoshi SAITO, Keiji IKEDA

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Abstract

A semiconductor memory device includes: a first via-wiring extending in a first direction; first semiconductor layers arranged in the first direction and electrically connected to the first via-wiring; memory portions arranged in the first direction and electrically connected to the first semiconductor layers; first gate electrodes arranged in the first direction and opposed to the plurality of first semiconductor layers; first wirings arranged in the first direction and electrically connected to the plurality of first gate electrodes; second semiconductor layers arranged in the first direction and electrically connected to the first wirings; second gate electrodes arranged in the first direction and opposed to the second semiconductor layers; a second via-wiring extending in the first direction and electrically connected to the plurality of second gate electrodes; and second wirings arranged in the first direction and electrically connected to the second semiconductor layers.

Claims16

Dependent claims

A semiconductor memory device comprising:

a substrate;
a first via-wiring extending in a first direction intersecting with a surface of the substrate;
a plurality of first semiconductor layers arranged in the first direction and electrically connected to the first via-wiring;
a plurality of memory portions arranged in the first direction and electrically connected to the plurality of first semiconductor layers;
a plurality of first gate electrodes arranged in the first direction and opposed to the plurality of first semiconductor layers;
a plurality of first wirings arranged in the first direction, extending in a second direction intersecting with the first direction, and electrically connected to the plurality of first gate electrodes;
a plurality of second semiconductor layers arranged in the first direction and electrically connected to the plurality of first wirings;
a plurality of second gate electrodes arranged in the first direction and opposed to the plurality of second semiconductor layers;
a second via-wiring extending in the first direction and electrically connected to the plurality of second gate electrodes;
and
a plurality of second wirings arranged in the first direction, extending in a third direction intersecting with the first direction and the second direction, and electrically connected to the plurality of second semiconductor layers.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/884,849Filed 13 Sep 2024
Priority: JP 2023-15251520 Sep 2023
Published: 20 Mar 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11C 5/06
Details of stores covered by group G11C11/00: arrangements for interconnecting storage elements electrically, e.g. by wiring
H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
G11C 11/2273
Auxiliary circuits: reading or sensing circuits or methods
H10B 12/48
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: data lines or contacts therefor

Family

US 12,694,908 B2Related patent
US 2025/0095692 A1This patent

From the US filing history. Foreign family members aren’t listed.

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