Hardware accelerator, processor, chip, and electronic device

A hardware accelerator, comprising:

• a processing element (PE) array, an internal buffer unit of the hardware accelerator, and a data scheduler between the PE array and the internal buffer unit;
• wherein the data scheduler is configured to:
• sequentially obtain multiple image lines to be processed from the internal buffer unit, and schedule the PE array to sequentially perform multiply-accumulate (MAC) operations on the multiple image lines, wherein overlapping pixel lines between adjacent image lines are subjected to MAC operations in both of the adjacent image lines to which they belong;
• and
• during the MAC operations on each image line, schedule the PE within the PE array that processes a current image line in tiles, to perform MAC operations on multiple tiles included in each image line, wherein for adjacent tiles, an operation result of the overlapping portion between a previous tile and a subsequent tile is cached, and combined with the operation result of the non-overlapping portion of the subsequent tile to form a MAC operation result of the subsequent tile.