Functional safety image signal processor

A system-on-chip (SoC) apparatus comprising:

• an image signal processor (ISP) pipeline that is connected and configure to receive and process input image data and to generate output image data;
• a checksum generator configured to generate a checksum value from the output image data;
• and
• a processing circuit that configures a configuration memory table with the one or more configurable edge pattern settings and corresponding input seed value and reference checksum value, where the processing circuit is further configured to:
• activate a test pattern generator to generate test pattern data by modulating a sequence of pseudo random number values with a sequence of values from an edge pattern;
• supply the test pattern data to the ISP pipeline as input image data which is processed by the ISP pipeline to output the output image data as ISP test output data;
• receive a checksum value generated from the ISP test output data by the checksum generator;
• and
• compare the checksum value with the reference checksum value to verify a functionality of the ISP pipeline.

A method for controlling a functional safety image signal processor comprising:

• generating an image signal processor (ISP) test pattern by modulating a plurality of pseudo random number values with a corresponding plurality of values from an edge pattern that includes edge structures;
• supplying the ISP test pattern to an ISP pipeline as input image data which is processed by the ISP pipeline to output ISP test output data;
• generating a checksum of the ISP test output data;
• and
• comparing the checksum with a previously generated checksum.