Qubit mapping method and apparatus, device, and storage medium

A computer device, comprising a processor and a memory, the memory having a computer program stored therein that, when loaded and executed by the processor, causes the computer device to implement a qubit mapping method including:

• obtaining a coupling graph corresponding to a quantum device, each vertex in the coupling graph representing one qubit in the quantum device, an edge between two vertexes representing that a two-qubit gate is allowed to directly act on qubits corresponding to the two vertexes;
• generating at least two connected subgraphs based on the coupling graph, a quantity of vertexes of each connected subgraph being greater than or equal to 2 and less than or equal to a routing number of the coupling graph, a sum of quantities of vertexes of the at least two connected subgraphs being equal to a constant multiple of a quantity of vertexes of the coupling graph, and the routing number of the coupling graph being a maximum quantity of permutation rounds of all permutations on the coupling graph;
• and
• performing qubit mapping on a logic circuit based on the at least two connected subgraphs, to obtain a hardware compilable circuit equivalent to the logic circuit.

A non-transitory computer-readable storage medium having a computer program stored therein that, when loaded and executed by a processor of a computer device, causes the computer device to implement a qubit mapping method including:

• obtaining a coupling graph corresponding to a quantum device, each vertex in the coupling graph representing one qubit in the quantum device, an edge between two vertexes representing that a two-qubit gate is allowed to directly act on qubits corresponding to the two vertexes;
• generating at least two connected subgraphs based on the coupling graph, a quantity of vertexes of each connected subgraph being greater than or equal to 2 and less than or equal to a routing number of the coupling graph, a sum of quantities of vertexes of the at least two connected subgraphs being equal to a constant multiple of a quantity of vertexes of the coupling graph, and the routing number of the coupling graph being a maximum quantity of permutation rounds of all permutations on the coupling graph;
• and
• performing qubit mapping on a logic circuit based on the at least two connected subgraphs, to obtain a hardware compilable circuit equivalent to the logic circuit.