US 2025/0094679 A1Published application

Low-level feedback-guided scheduling for high-level synthesis

AssigneeDeepMind Technologies Limited

InventorsZhigang Pan, Hanchen Ye, Xiaoqing Xu, Christopher Daniel Leary

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Abstract

The technology employs an iterative system of difference constraints (ISDC) approach that leverages low-level feedback from downstream tools to iteratively refine scheduling with respect to circuit design high-level synthesis. In each iteration, a number of subgraphs are extracted from an original computation graph and passed to selected downstream tools, e.g., for logic synthesis, placement and/or routing. The downstream tools' compilation results are extracted and fed back to a scheduler. With the feedback, the scheduler recalculates delay estimation between each pair of nodes in the original computation graph and prunes redundant scheduling constraints. As a result, the explorable design space is enlarged in the next iteration, leading to refined scheduling results. This feedback-guided approach is compatible with versatile design constraints and objectives, such as minimizing register usage given a targeted clock period, minimizing the clock period given a constrained area budget, etc., to provide improvements to the system operation.

Claims20

Dependent claims

A computer-implemented method, comprising:

creating, by one or more processors, an initial pipeline comprising a set of nodes, the initial pipeline corresponding to a function to be implemented by an integrated circuit according to a set of constraints, in which adjacent pairs of nodes are each associated with a corresponding timing constraint;
performing, by the one or more processors, subgraph extraction on the initial pipeline to obtain a set of combinational subgraphs;
providing, by the one or more processors, the set of combinational subgraphs to one or more downstream tools, the one or more downstream tools including at least one of a logic synthesis tool, a placement tool or a routing tool;
obtaining, by the one or more processors from the one or more downstream tools, a set of subgraph delays;
and
revising, by the one or more processors based on the obtained set of subgraph delays, the initial pipeline comprising the set of nodes to create an updated pipeline comprising an updated set of nodes, the updated pipeline corresponding to the function to be implemented by the integrated circuit according to the set of constraints, in which adjacent pairs of the updated set of nodes are each associated with a corresponding updated timing constraint.

3 more elements

A processing system, comprising:

memory configured to store information associated with fabrication of an integrated circuit;
and
one or more processors operatively coupled to the memory, the one or more processors configured to:
create an initial pipeline comprising a set of nodes, the initial pipeline corresponding to a function to be implemented by the integrated circuit according to a set of constraints, in which adjacent pairs of nodes are each associated with a corresponding timing constraint;
perform subgraph extraction on the initial pipeline to obtain a set of combinational subgraphs;
provide the set of combinational subgraphs to one or more downstream tools, the one or more downstream tools including at least one of a logic synthesis tool, a placement tool or a routing tool;
obtain, from the one or more downstream tools, a set of subgraph delays;
and
revise, based on the obtained set of subgraph delays, the initial pipeline comprising the set of nodes to create an updated pipeline comprising an updated set of nodes, the updated pipeline corresponding to the function to be implemented by the integrated circuit according to the set of constraints, in which adjacent pairs of the updated set of nodes are each associated with a corresponding updated timing constraint.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/825,059Filed 5 Sep 2024
Priority: 15 Sep 2023
Published: 20 Mar 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/3312
Using simulation: timing analysis
G06F 2119/12
Details relating to the type or aim of the analysis or the optimisation: timing analysis or timing optimisation
G06F
Computing and data processing

Family

Application63/538,525Us provisional application · filed 15 Sep 2023
US 2025/0094679 A1This patent

From the US filing history. Foreign family members aren’t listed.

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