Arithmetic processing device and operating method of arithmetic processing device

An arithmetic processing device comprising:

• a core group configured to include a plurality of cores each including a processor;
• a first memory configured to hold a matrix including a plurality of elements;
• a second memory configured to hold data obtained by transforming the elements in the matrix held in the first memory;
• and
• an accelerator configured to execute a matrix product operation,
• wherein each of the plurality of cores transforms elements in a plurality of submatrices into which the matrix is divided, writes data obtained by the transforming to the second memory, and then instruct the accelerator to execute the matrix product operation for the transformed data,
• wherein the accelerator executes, based on the instruction, the matrix product operation for the transformed data, and writes an execution result to the second memory,
• wherein, in a case where there is a submatrix that is not transformed among the plurality of submatrices, any of the plurality of cores performs the transformation, writing of the transformed data to the second memory, and an instruction to execute the matrix product operation for the transformed data, and
• wherein, in a case where the transformation of all of the plurality of submatrices is completed, the plurality of cores wait for completion of the matrix product operations by the accelerator.