Simt processor with storage having sets of storage locations corresponding to different threads of a parallel thread group to store data elements output from corresponding sets of registers of a register file

A single instruction, multiple thread (SIMT) processor comprising:

• an instruction unit to receive a SIMT instruction, the SIMT instruction having a first register index;
• a register file having a plurality of sets of registers, each of the plurality of sets of registers corresponding to a different thread of a parallel thread group;
• and
• a storage coupled with the register file, the storage having a plurality of sets of one or more data element storage locations, each of the plurality of sets of one or more data element storage locations corresponding to a different thread of the parallel thread group,
• wherein, based on the SIMT instruction:
• the register file is to output a copy of a first data element from a first register indicated by the first register index in each of the plurality of sets of registers;
• and
• the storage is to store each of the copies of the first data elements in the set of one or more data element storage locations for the corresponding thread.

A method performed by a single instruction, multiple thread (SIMT) processor, the method comprising:

• receiving a SIMT instruction, the SIMT instruction having a first register index;
• performing operations based on the SIMT instruction, including:
• outputting a copy of a first data element, from a first register indicated by the first register index, in each of a plurality of sets of registers a register file, wherein each of the plurality of sets of registers corresponds to a different thread of a parallel thread group;
• and
• outputting one or more data elements from each of a plurality of sets of one or more data element storage locations of a storage, wherein each of the plurality of sets of one or more data element storage locations corresponds to a different thread of the parallel thread group.