US 2025/0094374 A1Published application

Nand switch

AssigneeKioxia Corporation

InventorSie Pook LAW

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Abstract

In a memory system, a switch is connected between a controller and multiple non-volatile storage units, where the switch comprises first and second pins, a data bus, and a plurality of enable outputs. The switch is configured to transmit a signal to enable a communication path between the controller and one of the non-volatile storage units and to receive data over the data bus to be stored in one of the non-volatile storage units when the first and second pins are not asserted. In addition, the switch is configured to receive a command to be executed by one of the non-volatile storage units when the first pin is not asserted and the second pin is asserted. The switch is also configured to receive an address of a storage location within one of the non-volatile storage units when the first pin is asserted and the second pin is not asserted.

Claims20

Dependent claims

A memory system, comprising:

a controller including a first enable output and a data output;
a plurality of memories each including an enable input and a data input;
and
a plurality of electronic devices including a first device,
wherein each of the plurality of electronic devices is coupled with the controller, and the first device is coupled with each of a first set of the plurality of memories,
wherein the first device includes an enable input that is connectable to the first enable output of the controller, a data input that is connectable to the data output of the controller, a data output that is connectable to the data input of each of the first set of the plurality of memories, and a plurality of enable outputs that are each connectable to the enable input of a corresponding one of the first set of the plurality of memories, and
wherein the first device is configured to:
receive a first signal to assert the enable input of the first device;
receive a first command to identify a first selected memory of the first set of the plurality of memories for which the enable input is connectable to one of the plurality of enable outputs of the first device;
enable a communication path between the controller and the first selected memory;
receive, from the controller, a second command and an address of the first selected memory;
and
send, to the data input of the first selected memory, the second command and the address of the first selected memory.

10 more elements

A method of performing read and write operations in a memory system that comprises a controller, a plurality of memories, and a plurality of electronic devices including a first device, wherein the controller includes a first enable output and a data output, each of the plurality of memories includes an enable input and a data input, each of the plurality of electronic devices is coupled with the controller, the first device is coupled with each of a first set of the plurality of memories, and the first device includes an enable input that is connectable to the first enable output of the controller, a data input that is connectable to the data output of the controller, a data output that is connectable to the data input of each of the first set of the plurality of memories, and a plurality of enable outputs that are each connectable to the enable input of a corresponding one of the first set of the plurality of memories, the method comprising:

receiving, by the first device, a first signal to assert the enable input of the first device;
receiving, by the first device, a first command to identify a first selected memory of the first set of the plurality of memories for which the enable input is connectable to one of the plurality of enable outputs of the first device;
enabling, by the first device, a communication path between the controller and the first selected memory;
receiving, by the first device from the controller, a second command and an address of the first selected memory;
and
sending, by the first device to the data input of the first selected memory, the second command and the address of the first selected memory.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/972,748Filed 6 Dec 2024
Priority: 7 Feb 2014
Published: 20 Mar 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 13/40
Information transfer, e.g. on bus: bus structure
G06F 13/1668
For access to memory bus: details of memory controller
G06F
Computing and data processing

Family

Application14/175,269Continuation · filed 7 Feb 2014
Application16/726,763Continuation · filed 24 Dec 2019
Application17/406,989Continuation · filed 19 Aug 2021
Application18/321,685Continuation · filed 22 May 2023
Application18/972,748Continuation
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US 2023/0289308 A1Published application
US 2025/0094374 A1This patent

From the US filing history. Foreign family members aren’t listed.

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