US 2025/0094367 A1 · MULTI-BANK MEMORY THAT SUPPORTS MULTIPLE READS AND MULTIPLE WRITES PER CYCLE

Abstract

In a memory system having a plurality of memory banks, a plurality of memory access requests having a first priority level and a plurality of memory access requests having a second priority level different are received. A set of first memory banks executes the multiple memory access requests having the first priority level during a first clock cycle. The memory system determines one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle. In response to determining the one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle, the one or more second memory banks execute one or more memory access requests having the second priority level during the first clock cycle.

Claims23

Dependent claims

A memory system, comprising:

a plurality of memory banks;
and
circuitry configured to:
receive a plurality of memory access requests having a first priority level,
receive a plurality of memory access requests having a second priority level different than the first priority level,
forward multiple memory access requests having the first priority level to a set of first memory banks to be executed by the set of first memory banks during a first clock cycle,
determine one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle, and
in response to determining the one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle, forward one or more memory access requests to the one or more second memory banks to be executed by the one or more second memory banks during the first clock cycle.

5 more elements

A method for executing memory access requests by a memory system that includes a plurality of memory banks, the comprising:

receiving a plurality of memory access requests having a first priority level;
receiving a plurality of memory access requests having a second priority level different than the first priority level;
executing, by a set of first memory banks, multiple memory access requests having the first priority level during a first clock cycle;
determining, by the memory system, one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle;
and
in response to determining the one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle, executing, by the one or more second memory banks, one or more memory access requests having the second priority level during the first clock cycle.

3 more elements

Dependencies are inferred from the claim text.

Multi-bank memory that supports multiple reads and multiple writes per cycle

Life of this patent

Multi-bank memory that supports multiple reads and multiple writes per cycle

Life of this patent

Abstract

Claims23