Methods and apparatus to reduce bank pressure using aggressive write merging

A device comprising:

• a main cache memory;
• a victim cache memory;
• and
• a main cache queue coupled to the main cache memory and that includes:
• a first pipeline stage;
• a second pipeline stage that precedes the first pipeline stage;
• and
• a first circuit coupled to the first pipeline stage and the second pipeline stage and configured to:
• determine, based on an address associated with a first set of data and an address associated with a second set of data that are received for writing, whether to:
• cause the first set of data to be written to the main cache memory;
• or
• inhibit writing of the first set of data to the main cache memory and cause the first set of data to be merged with the second set of data to produce a third set of data.

A method comprising:

• receiving, by a cache queue, sets of data for writing to a cache memory that include a first set of data and a second set of data, wherein the cache queue includes a first pipeline stage and a second pipeline stage preceding the first pipeline stage;
• based on the first set of data being in the first pipeline stage and the second set of data being in the second pipeline stage, comparing a first address associated with the first set of data with a second address associated with the second set of data;
• and
• determining, based on comparison of the first address with the second address, whether to inhibit writing of the first set of data to the cache memory and cause the first set of data to be merged with the second set of data within the cache queue to produce a third set of data.