US 2025/0094356 A1 · VIRTUAL MEMORY PAGING SYSTEM AND TRANSLATION LOOKASIDE BUFFER WITH PAGELETS

Abstract

A page in a memory is sectioned into a plurality of pagelets (sub-pages) of sizes smaller than the page to speed up data transfers. The pagelets in the page are used to store, transport and process data, wherein individual pagelets are transferred between a memory and secondary storage in the system with smaller individual latencies than that of the page they comprise. Pagelets may be transferred in any order such that there is a reduction in the effective latency of the transfer of critical chunks of data as seen by an agent to increase overall performance. Pagelets of a page share one entry in a page table that also includes a virtual to physical translation. A pagelet translation lookaside buffer that handles pages having pagelets is used to cache frequently used translations and a critical pagelet determiner is used to indicate the critical pagelet involved in a transaction.

Claims28

Dependent claims

A system having a virtual memory comprising:

a memory having at least one page that comprises pagelets, wherein individual ones of the pagelets are associated with a same page number;
and
at least one page table comprising at least one first entry that comprises a virtual address to a physical address translation associated with the at least one page.

A method to probe a pagelet translation lookaside buffer, the method comprising:

presenting a virtual address to the pagelet translation lookaside buffer that handles pages having pagelets, obtaining a virtual page number, and matching with one or more entries in the pagelet translation lookaside buffer to obtain a matching entry;
reading one or more access control identifiers and a privilege level;
checking pagelet states of the matching entry for a valid pagelet present, and checking for a pagelet hit or a pagelet miss;
upon a pagelet hit, checking the one or more access control identifiers and privilege level against the matching entry and deciding to permit or deny access to the matching entry;
and
raising a protection failure when access to the matching entry is denied, or alternately when access is permitted, returning an entry number associated with the matching entry and matching entry contents.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/692,192Filed 5 Jun 2023

Priority

6 Jun 2022

Published

20 Mar 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 12/1027
Address translation: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/1081
Address translation: for peripheral access to main memory, e.g. direct memory access [DMA]
G06F 12/0802
In hierarchically structured memory systems, e.g. virtual memory systems: addressing of a memory level in which the access to the desired data or…
G06F 12/0808
Multiuser, multiprocessor or multiprocessing cache systems: with cache invalidating means

Virtual memory paging system and translation lookaside buffer with pagelets

Life of this patent

Virtual memory paging system and translation lookaside buffer with pagelets

Life of this patent

Abstract

Claims28