Design verification process for bit spreading error resistant memory system

A method for verification of a design of a memory, the method comprising:

• using, by a processor-based system, a bit spreading geometry file to convert a logical address of the memory to a physical address, wherein the bit spreading geometry file defines a bit spreading scheme by which data bits of a data word stored at the logical address are stored in a spread fashion over a plurality of random access memories (RAMs) of the memory;
• writing, by the processor-based system, data bits of a test data word to the physical address;
• causing, by the processor-based system, a design simulator to simulate a read from the logical address;
• and
• comparing, by the processor-based system, a result of the simulated read to the test data word to verify the design of the memory.

A method for verification of a design of a memory, the method comprising:

• using, by a processor-based system, a bit spreading geometry file to convert a logical address of the memory to a physical address, wherein the bit spreading geometry file defines a bit spreading scheme by which data bits of a data word stored at the logical address are stored in a spread fashion over a plurality of random access memories (RAMs) of the memory;
• causing, by the processor-based system, a design simulator to simulate a write of a test data word to the logical address of the memory;
• reading, by the processor-based system, data bits from the physical address;
• arranging, by the processor-based system, the data bits to form a retrieved data word;
• and
• comparing, by the processor-based system, the test data word to the retrieved data word to verify the design of the memory.