US 2025/0094333 A1 · MEMORY SYSTEM AND OPERATION METHOD THEREOF

Abstract

An example of the present application provides a memory system and an operation method thereof. In one example, the memory system includes a memory device; the operation method may include: in response to a write duty cycle adjustment (WDCA) being performed for a data strobe (DQS) signal of the memory device, configuring an adjustment code that adjusts the duty cycle of the DQS signal; the adjustment code represents the step size of adjustment for adjusting the duty cycle of the DQS signal; generating an adjustment signal in accordance with the adjustment code; adjusting the duty cycle of the DQS signal in accordance with the adjustment signal.

Claims20

Dependent claims

A method for operating a memory system including a memory device, comprising:

in response to a write duty cycle adjustment (WDCA) being performed for a data strobe (DQS) signal of the memory device, configuring an adjustment code that adjusts a duty cycle of the DQS signal, wherein the adjustment code represents a step size of adjustment for adjusting the duty cycle of the DQS signal;
generating an adjustment signal in accordance with the adjustment code;
and
adjusting the duty cycle of the DQS signal in accordance with the adjustment signal.

1 more element

A memory system, including:

a memory controller that is coupled to one or more memory devices, wherein the memory controller is configured to control the one or more memory devices, and the memory controller is configured to:
in response to a write duty cycle adjustment (WDCA) being performed for a write data strobe (DQS) signal of the memory device, configure an adjustment code that adjusts the duty cycle of the DQS signal into the memory device, wherein the adjustment code represents a step size of adjustment for adjusting the duty cycle of the DQS signal;
and
wherein the one or more memory devices are configured to:
obtain the adjustment code;
generate an adjustment signal in accordance with the adjustment code;
and
adjust the duty cycle of the DQS signal in accordance with the adjustment signal.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/437,333Filed 9 Feb 2024

Priority

CN 202311229338.X20 Sep 2023

Published

20 Mar 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G11C 29/028
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: with adaption or trimming of parameters
G11C 29/023
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in clock generator or timing circuitry
G11C 29/50012
Marginal testing, e.g. race, voltage or current testing: of timing

Memory system and operation method thereof

Life of this patent

Memory system and operation method thereof

Life of this patent

Abstract

Claims20