Storage system and data center including the same

A data center comprising:

• a plurality of application servers configured to receive a data write request or a data read request;
• and
• a plurality of storage servers configured to store write data corresponding to the data write request or to output read data corresponding to the data read request,
• wherein a first storage server among the plurality of storage servers includes:
• a plurality of first dynamic random access memory (DRAM)-less storage devices, each of the plurality of first DRAM-less storage devices including a plurality of nonvolatile memories;
• at least one first compute express link (CXL) memory expander electrically connected to the plurality of first DRAM-less storage devices, the at least one first CXL memory expander configured to communicate through a CXL interface and to operate as a buffer memory of the plurality of first DRAM-less storage devices;
• and
• a first power loss protection (PLP) capacitor electrically connected to the plurality of first DRAM-less storage devices and the at least one first CXL memory expander and disposed outside the plurality of first DRAM-less storage devices, the first PLP capacitor configured to supply an auxiliary power voltage to the plurality of first DRAM-less storage devices and the at least one first CXL memory expander in a sudden power-off (SPO) condition,
• wherein the at least one first CXL memory expander includes a first memory region allocated for the plurality of first DRAM-less storage devices, and
• wherein the first memory region is configured to store mapping data including mapping information corresponding to a plurality of user data stored in the plurality of nonvolatile memories included in the plurality of first DRAM-less storage devices.

A storage system comprising:

• a host device;
• a plurality of quadruple-level cell (QLC) dynamic random access memory (DRAM)-less storage devices controlled by the host device, each of the plurality of QLC DRAM-less storage devices including a plurality of QLC nonvolatile memories including a plurality of QLCs configured to store 4-bit data as a storage medium;
• at least one compute express link (CXL) memory expander controlled by the host device and electrically connected to the plurality of QLC DRAM-less storage devices, the at least one CXL memory expander configured to communicate through a CXL interface and to operate as a buffer memory of the plurality of QLC DRAM-less storage devices;
• at least one accelerator electrically connected to the plurality of QLC DRAM-less storage devices and the at least one CXL memory expander and formed separately from the host device, the at least one accelerator configured to perform a data processing function, and to perform at least one of an erasure code function and an end-to-end data protection function for the plurality of QLC DRAM-less storage devices;
• and
• a power loss protection (PLP) capacitor electrically connected to the plurality of QLC DRAM-less storage devices and the at least one CXL memory expander and disposed outside the plurality of QLC DRAM-less storage devices, the PLP capacitor configured to supply an auxiliary power voltage to the plurality of QLC DRAM-less storage devices and the at least one CXL memory expander in a sudden power-off (SPO) condition,
• wherein the at least one CXL memory expander includes:
• a first memory region for the plurality of QLC DRAM-less storage devices;
• and
• a second memory region configured to be accessed and managed by the host device,
• wherein the first memory region is configured to store mapping data including mapping information corresponding to a plurality of user data stored in the plurality of QLC nonvolatile memories included in the plurality of QLC DRAM-less storage devices,
• wherein the at least one accelerator includes at least one nonvolatile memory, and
• wherein, in the SPO condition, data stored in the at least one CXL memory expander is flushed to the at least one nonvolatile memory included in the at least one accelerator.