Method for low latency fail-operational time sensitive networking

An apparatus, comprising:

• a network interface controller (NIC), including:
• circuitry to implement an Ethernet transmit and receive pipeline, including a Serializer/Deserializer (SERDES) block, a plurality of Media Access Channel (MAC) blocks coupled to respective Physical Coding Sublayer (PCS) blocks;
• Static Random Access Memory (SRAM);
• an input/output (I/O) interface;
• and
• an error detection and path switching (EDPS) circuit having an output coupled
• to the SERDES block and each of the plurality of MAC blocks and each of the respective PCS blocks, the EDPS circuit configured to:
• read data from SRAM,
• detect whether read data is errant, the errant data including one or more uncorrectable errors;
• when errant data is detected,
• read or receive correct data comprising a correct copy of the errant data via the I/O interface;
• and
• enable the correct data to be read by one or more of the SERDES block, the plurality of MAC blocks and the respective PCS blocks.

A method implemented by a Network Interface Controller (NIC), comprising:

• writing data including boot code stored in a non-volatile memory device into volatile memory on the NIC,
• in response a read request from a read requestor to read data from the volatile memory,
• performing an error correction code (ECC) check to determine whether the read data, has no ECC errors;
• has one or more correctable single-bit errors;
• or
• comprises errant uncorrectable data including one or more uncorrectable errors;
• comprises errant data including one or more uncorrectable errors,
• has one of no ECC errors, one or more correctable single bit errors, or one or more uncorrectable errors;
• when it is determined the read data comprises errant uncorrectable data,
• access correct data comprising a correct copy of the errant uncorrectable data from the non-volatile memory device;
• and
• provide the correct data to the read requestor.