System Cache Path To Enable Path-To-DDR Infrastructure Scan Dump During Device Crashes

A computing device, comprising:

• a memory subsystem comprising:
• a plurality of memory subsystem cores;
• at least one memory controller having at least one scan dump logic module, at least one memory logic module, at least one low power logic module, and at least one cache;
• a scan dump network on chip (NoC) module;
• a memory path bus configured to connect a memory NoC module and the at least one memory logic module;
• a low power memory path bus configured to connect a low power NoC module and the at least one low power logic module;
• and
• a scan dump path bus configured to connect the scan dump NoC module and the at least one scan dump logic module;
• and
• a microcontroller configured to:
• enable a scan dump path of the memory subsystem during a computing device crash reset flow, the scan dump path comprising the at least one scan dump logic module, the scan dump NoC module, and the scan dump path bus;
• and
• initialize a scan mode for a memory path of the memory subsystem and for a low power memory path of the memory subsystem, the memory path including the memory NoC module, the at least one memory logic module, and the memory path bus, and the low power memory path including the low power NoC module, the at least one low power logic module, and the low power memory path bus.