PERFORMING DYNAMIC MICROARCHITECTURAL THROTTLING OF PROCESSOR CORES BASED ON QUALITY-OF-SERVICE (QoS) LEVELS IN PROCESSOR DEVICES

A processor device, comprising:

• means for determining a performance state of a processor core of a plurality of processor cores of a synchronous core cluster of the processor device;
• means for receiving, from the processor core, a Quality-of-Service (QOS) level associated with a workload scheduled for execution by the processor core;
• means for determining a throttling level for the processor core, based on the QoS level and the performance state;
• and
• means for performing microarchitectural throttling of the processor core based on the throttling level.

A method for performing dynamic microarchitectural throttling in processor cores based on Quality-of-Service (QOS) levels, comprising:

• determining, by a throttling selection circuit of a synchronous core cluster of a processor device, a performance state of a processor core of a plurality of processor cores of the synchronous core cluster;
• receiving, by the throttling selection circuit, a QoS level associated with a workload scheduled for execution by the processor core;
• determining, by the throttling selection circuit, a throttling level for the processor core, based on the QoS level and the performance state;
• providing, by the throttling selection circuit, the throttling level to a throttling circuit of the synchronous core cluster;
• receiving, by the throttling circuit, the throttling level;
• and
• performing, by the throttling circuit, microarchitectural throttling of the processor core based on the throttling level.

A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed, cause a processor device of a processor-based device to:

• determine a performance state of a processor core of a plurality of processor cores of a synchronous core cluster of the processor device;
• receive a Quality-of-Service (QOS) level associated with a workload scheduled for execution by the processor core;
• determine a throttling level for the processor core, based on the QoS level and the performance state;
• and
• perform microarchitectural throttling of the processor core based on the throttling level.