Processor with out-of-order completion
AssigneeApple Inc.
InventorAlon YAAKOV
Life of this patent
Estimating the term…
Abstract
A processor circuit that allows for out-of-order completion of instructions is disclosed. A processor circuit may fetch multiple instructions from a memory circuit. As individual instructions are fetched, the processor circuits checks for any hazards associated with the fetched instructions. Once it has been determined that there are no hazards for a particular instruction, it is issued to one of multiple execution circuits in the processor circuit. The processor circuit can complete instructions in an order in which the instructions finish execution by updating its architectural state with corresponding results of the instructions.
Claims20
An apparatus, comprising:
- an instruction memory circuit configured to store a plurality of instructions;
- a plurality of execution circuits;
- and
- a program sequencer circuit configured to:
- fetch the plurality of instructions from the instruction memory circuit in a program order;
- and
- issue a particular instruction to a particular execution circuit in response to a determination that there are no hazards associated with the particular instruction;
- and
- wherein the particular execution circuit is configured to complete the particular instruction prior to a completion of a different instruction of the plurality of instructions that was issued to a different execution circuit of the plurality of execution circuits prior to when the particular instruction was issued to the particular execution circuit.
A method, comprising:
- fetching, by a processor circuit, a plurality of instructions from a memory circuit;
- issuing, by the processor circuit, one or more instructions of the plurality of instructions to corresponding ones of a plurality of execution circuits included in the processor circuit in response to determining there are no pending hazards for the one or more instructions;
- and
- completing, by the processor circuit, the one or more instructions prior to completing a different instruction of the plurality of instructions, wherein the different instruction was issued to a different execution circuit of the plurality of execution circuits prior to when the one or more instructions were issued to the corresponding ones of the plurality of execution circuits.
An apparatus, comprising:
- a memory circuit configured to store a plurality of instructions;
- and
- a plurality of processor cores including a particular processor core configured to:
- fetch the plurality of instructions from the memory circuit;
- issue, to a particular execution circuit of a plurality of execution circuits included in the particular processor core, a particular instruction of the plurality of instructions in response to determining that there are no pending hazards for the particular instruction;
- and
- complete the particular instruction prior to completing a different instruction of the plurality of instructions, wherein the different instruction was issued to a different execution circuit of the plurality of execution circuits prior to when the particular instruction was issued to the particular execution circuit.
Dependencies are inferred from the claim text.