Multiple host memory controller

A controller, comprising:

• a first processor interface to receive a first memory command to write first data received via the first processor interface via a memory device interface;
• a second processor interface to receive a second memory command to read the first data;
• first write buffer circuitry to, based on the first memory command, store the first data at least until the first data is written via the memory device interface;
• and
• circuitry to, based on the second memory command, retrieve the first data from the first write buffer circuitry and transmit the first data via the second processor interface.

A controller, comprising:

• first write buffer circuitry to store first data received via a first processor interface;
• second write buffer circuitry to store second data received via a second processor interface;
• and
• the first processor interface to receive a first command that retrieves the second data from the second write buffer circuitry.

A method of operating a controller, comprising:

• via a first processor interface, receiving a first memory command to write first data received via the first processor interface via a memory device interface;
• via a second processor interface, receiving a second memory command to read the first data;
• based on the first memory command, storing, in first write buffer circuitry, the first data at least until the first data is written via the memory device interface;
• based on the second memory command, retrieving the first data from the first write buffer circuitry;
• and
• based on the second memory command, transmitting the first data via the second processor interface.