Flash memory controller and methods for executing cache erase operation

Abstract

A flash memory controller and a method for executing a cache erase operation are provided. The flash memory controller includes a first interface circuit and a processor. The first interface circuit is coupled to a flash memory to transmit data and commands. The processor is coupled to the first interface circuit to access the flash memory. The processor controls the first interface circuit to transmit a first command sequence and a second command sequence to the flash memory. The first command sequence includes a first command and a second command. In response to the transmission of the second command, the flash memory performs an erase operation. When the array ready status bit is in a non-ready status, the second command sequence is transmitted to the flash memory, so that related operations that will use a bus are performed while executing the erase operation to improve transmission efficiency.

Dependencies are inferred from the claim text.