Efficient Command Protocol
AssigneeMicron Technology, Inc.
InventorKang-Yong Kim
Life of this patent
Estimating the term…
Abstract
This document describes apparatuses and techniques for an efficient command protocol for memory access. In various aspects, a memory controller may implement combined operations of different command types (e.g., an activation command plus a read, an activation command plus a write, or an activation command plus a pre-charge command) to better utilize a multiple clock ratio of a command bus (e.g., a (1.5+0.5) N operation in a dual clocking WCK2CK ratio of 4:1), which may improve utilization of a data bus for associated memory responses. By so doing, the efficient command protocol may improve power efficiency and system level performance of a computing system.
Claims20
A method comprising:
- combining a first memory command of a host with a second memory command of the host to provide a combined memory command that is a multiple of a period of a clock at which a command bus of the host operates;
- communicating, via the command bus, the combined memory command to a memory device;
- and
- receiving, responsive to the combined memory command and via a data bus, a response from the memory device comprising a series of contiguous bits on the data bus.
An apparatus comprising:
- a queue to receive commands from a host;
- an interface for a memory interconnect comprising a command bus and a data bus;
- and
- a command processor configured to:
- combine a first memory command of the host with a second memory command of the host to provide a combined memory command that is a multiple of a period of a clock at which the command bus of the memory interconnect operates;
- communicate, via the command bus, the combined memory command to a memory device coupled to the memory interconnect;
- and
- receive, responsive to the combined memory command and via the data bus, a response from the memory device comprising a series of contiguous bits on the data bus.
A system comprising:
- a memory device comprising an array of memory cells;
- a memory interconnect coupled to the memory device, the memory interconnect comprising a command bus and a data bus;
- and
- a memory controller coupled to the memory interconnect, the memory controller configured to:
- combine a first memory command of a host with a second memory command of the host to provide a combined memory command that is a multiple of a period of a clock at which the command bus of the memory interconnect operates;
- communicate, via the command bus, the combined memory command to the memory device coupled to the memory interconnect;
- and
- receive, responsive to the combined memory command and via the data bus, a response from the memory device comprising a series of contiguous bits on the data bus.
Dependencies are inferred from the claim text.