Memory device and operating method thereof

A memory device comprising:

• a buffer die configured to transmit and receive data to and from a host device, wherein the buffer die includes a plurality of registers;
• a plurality of memory dies that are stacked on the buffer die, wherein the plurality of memory dies include a plurality of memory banks;
• and
• a plurality of through silicon vias that electrically connect the buffer die to respective ones of the plurality of memory dies,
• wherein the buffer die further comprises a control logic configured to receive a low latency bit and an address that is preset according to a type of the data,
• wherein the control logic is configured to determine a logic level of the low latency bit, and
• wherein, based on the low latency bit, the memory device is configured to store the data in a memory bank corresponding to the address among the plurality of memory banks or store the data in a register corresponding to the address among the plurality of registers, or read the data from the memory bank corresponding to the address or the register corresponding to the address.

An operating method of a memory device, comprising:

• receiving, by a memory device that comprises a buffer die including a plurality of registers and at least one memory die stacked on the buffer die and including a plurality of memory banks, data, a low latency bit that is preset according to a type of the data, a command, and an address from a host device;
• and
• determining a logic level of the low latency bit,
• wherein when the command is a write command, the operating method of the memory device comprises:
• mapping the address to at least one register address among a plurality of register addresses when the logic level of the low latency bit is at a first level;
• generating a mapping table including a mapping relationship between the address and the register address;
• and
• storing the data in a register corresponding to the mapped register address.