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US 2025/0094044 A1Published application
Multicore shared cache operation engine
AssigneeTexas Instruments Incorporated
InventorsKai Chirca, Matthew David Pierson, David E. Smith, Timothy David Anderson
Life of this patent
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Abstract
Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.
Claims20
A system comprising:
- an interface;
- and
- a controller coupled to the interface and configurable to:
- receive a first memory command via the interface to perform a first memory operation;
- receive a first event from the interface;
- and
- output the first memory command to perform the first memory operation in response the first event.
4 more elements
A system comprising:
- a system bus;
- and
- a memory controller coupled to the system bus and including:
- a local bus;
- a buffer configured to store:
- a first memory command to perform a first memory operation;
- and
- a second memory command to perform a second memory operation,
- wherein the memory controller is configurable to:
- receive a first set of bits from the system bus;
- detect a second set of bits on the local bus;
- output the first memory command to perform the first memory operation in response to the first set of bits;
- and
- output the second memory command to perform the second memory operation in response to the second set of bits.
11 more elements
Dependencies are inferred from the claim text.