Multi-Processor Power Management Circuit

A method comprising:

• executing, by a first processor circuit in an integrated circuit (IC), a control loop to monitor performance of a plurality of circuit blocks in the IC;
• determining, by the first processor circuit executing the control loop, requested performance states for a plurality of power domains included in the IC;
• executing, by a second processor circuit in the IC, firmware that is specific to a given instance of the IC;
• and
• controlling, by the second processor circuit using the requested performance states, sequencing of performance states among the plurality of power domains within the IC, wherein the sequencing avoids illegal performance state transitions.

An apparatus comprising:

• a power management circuit including:
• a first computer accessible storage medium storing instructions comprising one or more operating system control loops executable to monitor and manage power and performance in a system, wherein the control loops establish requested performance states for a plurality of power domains in the apparatus;
• a first processor configured to execute the one or more operating system control loops;
• a second computer accessible storage medium storing instructions comprising firmware that is specific to a given implementation of the system and that controls sequencing of performance states among the plurality of power domains within the apparatus based on the performance states requested by the control loops;
• and
• a second processor configured to execute the firmware and control hardware circuitry to perform the sequencing.