Shared connectivity manager (scm) operates in low power and high performance mode

An apparatus comprising:

• an integrated circuit comprising:
• first and second microcontroller units (MCUs);
• a data bus coupled to the first and second MCUs;
• wherein the first MCU is configured to send a first inter processor communication (IPC) message to the second MCU in response to the first MCU receiving and accepting a first message to establish a network data connection with an endpoint;
• wherein the first MCU is configured to transition from active mode to sleep mode after the first MCU sends the first IPC message to the second MCU;
• wherein the second MCU is configured to transition from sleep mode to active mode in response to the second MCU receiving the first IPC message;
• wherein the second MCU is configured to respond to the first message while operating in active mode.

An apparatus comprising:

• an integrated circuit comprising:
• a memory for storing instructions;
• first and second microcontroller units (MCUs) that can operate in active and sleep modes;
• wherein the first MCU is configured to execute the instructions only when the first MCU operates in active mode;
• wherein the second MCU is configured to execute the instructions only when the second MCU operates in active mode;
• the first MCU can accept a first message from an endpoint for establishing a network connection in response to executing instructions stored in the memory;
• wherein the first MCU is configured to transition from active mode to sleep mode after the first MCU accepts the first message;
• wherein the second MCU is configured to transition from sleep mode to active mode after the first MCU accepts the first message;
• wherein the second MCU is configured to transmit data to or receive data from the endpoint while operating in active mode and executing instructions stored in the memory.