US 2025/0093932 A1 · MEMORY HIERARCHY POWER MANAGEMENT

Abstract

Some embodiments include a system, apparatus, method, and computer program product for memory hierarchy power management. Some embodiments include a performance controller that balances memory hierarchy power and compute power to maintain package-level power efficiency of a systems-on-a-chip (SoC)-memory package. The performance controller can determine a ratio of memory hierarchy power to compute agent power, compare the ratio against a threshold value, and based on the comparison, determine how to manage memory hierarchy power. When the energy costs of the memory hierarchy power are large relative to the energy costs of the compute agent power, some embodiments include changing a performance state of a fabric and/or memory to increase the power efficiency of the overall SoC-memory package, even though a number of memory stall cycles experienced by the compute agent may increase.

Claims20

Dependent claims

A method for operating a systems-on-a-chip (SoC)-memory package comprising a compute agent, a memory, and a fabric interconnecting the compute agent and the memory, the method comprising:

monitoring a first ratio of memory power of the memory to compute power of the compute agent;
determining that the first ratio satisfies a first threshold value;
and
changing a memory performance state from a first memory dynamic voltage frequency management (DVFM) state to a second memory DVFM state, responsive to the determining the first ratio, wherein the compute agent experiences an increase in a number of memory stall cycles based at least on the second memory DVFM state, and wherein the changing the memory performance state increases a power efficiency of the SoC-memory package.

1 more element

A non-transitory computer-readable medium storing instructions that, upon execution by one or more processors of a systems-on-a-chip (SoC)-memory package comprising the one or more processors, a memory, and a fabric interconnecting the one or more processors and the memory, cause the SoC-memory package to perform operations, the operations comprising:

monitoring a first ratio of memory power of the memory to compute power of the one or more processors;
determining that the first ratio satisfies a first threshold value;
and
changing a memory performance state from a first memory dynamic voltage frequency management (DVFM) state to a second memory DVFM state, responsive to the determining the first ratio, wherein the one or more processors experience an increase in a number of memory stall cycles based at least on the second memory DVFM state, and wherein the changing the memory performance state increases a power efficiency of the SoC-memory package.

1 more element

A systems-on-a-chip (SoC)-memory package comprising:

a memory;
and
one or more processors communicatively coupled to the memory via a fabric, wherein the one or more processors are configured to:
monitor a first ratio of memory power of the memory to compute power of the compute agent;
determine that the first ratio satisfies a first threshold value;
and
change a memory performance state from a first memory dynamic voltage frequency management (DVFM) state to a second memory DVFM state, responsive to the determining the first ratio, wherein the compute agent experiences an increase in a number of memory stall cycles based at least on the second memory DVFM state, and wherein the changing the memory performance state increases a power efficiency of the SoC-memory package.

4 more elements

Dependencies are inferred from the claim text.

Memory hierarchy power management

Life of this patent

Memory hierarchy power management

Life of this patent

Abstract

Claims20