Duty correction circuit, a clock generation circuit and a semiconductor apparatus using the duty correction circuit

A clock generation circuit comprising:

• a phase delay circuit configured to receive a reference clock signal and delay the reference clock signal to generate a delay-locked clock signal;
• a first delay circuit configured to receive the delay-locked clock signal and delay the delay-locked clock signal to generate a first delayed clock signal;
• a second delay circuit configured to receive the delay-locked clock signal and variably delay the delay-locked clock signal to generate a second delayed clock signal based on a delay control signal;
• a dividing circuit configured to divide the first delayed clock signal to generate a first phase clock signal and a third phase clock signal, and configured to divide the second delayed clock signal to generate a second phase clock signal and a fourth phase clock signal;
• a clock gating circuit configured to gate the first to fourth phase clock signals to generate a first gating clock signal, a second gating clock signal, a third gating clock signal, a fourth gating clock signal, a fifth gating clock signal, a sixth gating clock signal, a seventh gating clock signal, and an eighth gating clock signal;
• a duty detector configured to generate a first output signal and a second output signal based on the first to eighth gating clock signals, and configured to compare the first and second output signals to generate a duty detection signal;
• and
• a delay control signal generation circuit configured to generate the delay control signal based on the duty detection signal.