Methods for making semiconductor-based integrated circuits

A method for making a semiconductor-based integrated circuit, the method comprising:

• placing a first schematic symbol associated with a plurality of front-end-of-line (FEOL) sections of the semiconductor-based integrated circuit fabricated with a silicon-photonics process;
• placing the first schematic symbol between a second schematic symbol and a third schematic symbol that are associated with a first back-end-of-line (BEOL) section and a second BEOL section of the semiconductor-based integrated circuit fabricated with a non-silicon-photonics process;
• obtaining a first length measured along a first direction and a second length measured along a second direction of a layout pattern corresponding to the first schematic symbol;
• and
• fabricating, in response to a determination that the first length and the second length are integer multiples of a layout grid size associated with the non-silicon-photonics process, the semiconductor-based integrated circuit at least partly based on the layout pattern corresponding to the first schematic symbol.

A system comprising a non-transitory computer-readable medium storing program instructions;

• and a processor operatively coupled to the non-transitory computer-readable medium, wherein the program instructions, when executed by the processor, cause the processor to perform:
• creating a first schematic instance of a plurality of front-end-of-line (FEOL) sections associated with a semiconductor-based integrated circuit using a silicon-photonics process, wherein the first schematic instance is associated with a first dimension;
• creating a second schematic instance of a first back-end-of-line (BEOL) section and a second BEOL section associated with the semiconductor-based integrated circuit using a non-silicon-photonics process, wherein the second schematic instance is associated with a second dimension, wherein the non-silicon-photonics process is associated with a second critical dimension that is larger than a first critical dimension associated with the silicon-photonics process;
• connecting the first schematic instance to the second schematic instance;
• determining whether a combined dimension of the first schematic instance and the second schematic instance is suitable for applying the non-silicon-photonics process;
• and
• converting, in response to a determination that the combined dimension of the first schematic instance and the second schematic instance is suitable for applying the non-silicon-photonics process, the first schematic instance and the second schematic instance into a layout.