Scan Data Transfer Circuits for Multi-die Chip Testing

A method comprising:

• shifting, through a particular set of scan-enabled flip-flop circuits included in a first clock domain of a circuit, a scan-chain pattern from a first test input pin to a first test output node;
• enabling, at a first point in time, a particular lockup latch to increase a propagation delay of the scan-chain pattern from the first test output node to a second test input node that is coupled to an input terminal of a given scan-enabled flip-flop circuit in a second clock domain of the circuit;
• and
• disabling, at a second point in time, the particular lockup latch to decrease the propagation delay of the scan-chain pattern from the first test output node to the second test input node;
• wherein the enabling and disabling are performed based on a clock skew between the first clock domain and the second clock domain.

A system comprising:

• a first integrated circuit (IC) including:
• a first set of scan-enabled flip-flop circuits configured to shift a scan-chain pattern from a first test input pin to a first test output node;
• a first input clock pin coupled to ones of the first set of scan-enabled flip-flop circuits;
• and
• a first lockup latch coupled to the first test output node and to a first test output pin, and configured to, when enabled, delay propagation of the scan-chain pattern from the first test output node to the first test output pin;
• and
• a second IC including:
• a second set of scan-enabled flip-flop circuits configured to shift the scan-chain pattern from a second test input pin to a second test output node;
• a second input clock pin coupled to ones of the second set of scan-enabled flip-flop circuits;
• and
• a second lockup latch coupled to the second test output node and to a second test output pin, and configured to, when enabled, delay propagation of the scan-chain pattern from the second test output node to the second test output pin;
• and
• wherein the first test output pin is coupled to the second test input pin.