Memory control system and memory control method for reducing memory traffic
AssigneeMediatek Inc.
InventorsHsing-Chuang Liu, Cheng-Chih Hsiao, Hsien-Hua Hsieh
Life of this patent
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Abstract
A memory control method includes a processor initiating a memory access instruction to a cache controller to search a cache memory, an address detector checking if the memory access instruction is corresponding to predetermined conditions if a cache miss occurs, the address detector transmitting a signal to inform a replacement mask logic unit if the memory access instruction is corresponding to the predetermined conditions, and the replacement mask logic unit providing predetermined data to store the predetermined data into the cache memory.
Claims20
A memory control method after a cache controller processing a memory access instruction to search a cache memory and a cache miss occurs, comprising,
- checking, by an address detector, if the memory access instruction corresponds to predetermined conditions;
- transmitting, by the address detector, a signal to inform a replacement mask logic unit while the memory access instruction corresponds to the predetermined conditions;
- and
- providing, by the replacement mask logic unit, predetermined data to store the predetermined data into the cache memory.
A memory control system comprising:
- a processor configured to initiate a memory access instruction;
- a cache memory;
- a cache controller coupled to the processor and the cache memory and configured to receive the memory access instruction to search the cache memory and transmit a first signal if the a cache miss occurs;
- a bus transaction controller coupled to the cache controller and configured to receive the first signal, and transmit a second signal corresponding to the first signal;
- an address detector coupled to the bus transaction controller and configured to receive the second signal, check if the memory access instruction is corresponding to predetermined conditions, and transmit a third signal if the memory access instruction is corresponding to the predetermined conditions;
- and
- a replacement mask logic unit coupled to the address detector and the bus transaction controller and configured to receive the third signal and provide predetermined data to the bus transaction controller to store the predetermined data into the cache memory.
Dependencies are inferred from the claim text.