Processing Memory Access Transactions
OwnerPeter Vrabel, Jack Andrew +1inventors
InventorsPeter Vrabel, Jack Andrew, Ravindranath Ramalingaiah Mannan
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OwnerPeter Vrabel, Jack Andrew +1inventors
InventorsPeter Vrabel, Jack Andrew, Ravindranath Ramalingaiah Mannan
Estimating the term…
A memory attribute structure comprises one or more memory address entries. Each memory address entry comprising a respective memory address range mapped to a respective priority level. The memory attribute table is used when processing a memory access transaction through an execution path of a processing system. During said processing, a memory address of the memory access transaction is determined. The memory attribute structure is used to determine a priority level mapped to the determined memory address, and the memory access transaction is processed based on the determined priority level.
A method of processing a memory access transaction through an execution path of a processing system, wherein a memory attribute structure comprises one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels, the method comprising:
A non-transitory computer-readable storage medium having computer code stored thereon, which when run on a processing system, causes the processing system to process a memory access transaction through an execution path of the processing system, wherein a memory attribute structure comprises one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels, and wherein said processing a memory access transaction comprises:
A processing system for processing a memory access transaction through an execution path of the processing system, wherein the processing system has stored, in memory, a memory attribute structure comprising one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels, the processing system being configured to:
Dependencies are inferred from the claim text.