Computing apparatus and method for executing convolution operation, and related products
AssigneeCambricon (Xi'an) Semiconductor Co., Ltd.
InventorsYufeng GAO, Jinhua TAO
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AssigneeCambricon (Xi'an) Semiconductor Co., Ltd.
InventorsYufeng GAO, Jinhua TAO
Estimating the term…
A computing apparatus, a method of performing a convolution operation utilizing the computing apparatus, and related products are described. The computing apparatus is included in a combined processing apparatus. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a user specified computation operation. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the computing apparatus and other processing apparatus. The described techniques optimize the convolution operation to improve data reuse efficiency, thereby improving computational processing efficiency.
A computing apparatus, comprising a plurality of slave processing circuits, wherein each slave processing circuit includes a first caching circuit, a second caching circuit, and a plurality of computing circuits, wherein
A chip, comprising a computing apparatus, wherein the computing apparatus comprises a plurality of slave processing circuits, wherein each slave processing circuit includes a first caching circuit, a second caching circuit, and a plurality of computing circuits, wherein
(canceled)
A method for using a computing apparatus of to perform a convolution operation, wherein the computing apparatus comprises a plurality of slave processing circuits, wherein each slave processing circuit includes a first caching circuit, a second caching circuit, and a plurality of computing circuits, wherein the first caching circuit is used to cache a plurality of input feature lines on which a convolution operation is to be performed, wherein one of the input feature lines includes the data amount of Pci×Ws=M in an input feature map, where Pci is a slice granularity of a Ci dimension of an input channel, Ws is a folding multiplier of a W dimension of the width, and M is the amount of data processed by hardware at one time;
Dependencies are inferred from the claim text.