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AssigneeIntel Corporation
InventorsShuai Mu, Supratim Pal, Pradeep Golconda, Srilakshmi Jammula, Jiasheng Chen
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An apparatus to facilitate unblocking the integer pipeline during math pipeline phases in a graphics environment is disclosed. The apparatus includes an execution resource comprising: a thread arbiter; a plurality of execution pipeline hardware circuitry comprising a math execution pipeline and an integer execution pipeline to share resources of the thread arbiter; arbitration hardware circuitry to determine whether the math execution pipeline is available for loading math operand data of a math instruction; and a math instruction staging buffer to store the math operand data responsive to the math execution pipeline not being available; wherein the integer execution pipeline is to receive integer operand data for an integer instruction while bypassing the math operand data in the math instruction staging buffer; and wherein the math execution pipeline is to receive, responsive to the math execution pipeline becoming available, the math operand data from the math instruction staging buffer.
A processor comprising:
A method comprising:
A non-transitory computer-readable medium having instructions stored thereon, which when executed by one or more processors, cause the processors to:
Dependencies are inferred from the claim text.