Inductors using nand layers
AssigneeMicron Technology, Inc.
InventorsSrivatsan Venkatesan, Kaveri Jain, Salil Shashikant Mujumdar, Rajat Vishnoi, Sushma Dogiparthi
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AssigneeMicron Technology, Inc.
InventorsSrivatsan Venkatesan, Kaveri Jain, Salil Shashikant Mujumdar, Rajat Vishnoi, Sushma Dogiparthi
Estimating the term…
An inductor is formed on an integrated circuit (IC) using one or more structures formed during or in coordination with 3D NAND structure fabrication with one or more modifications. The inductor has a staircase structure, the staircase structure having a plurality of tiers that form steps on one side of the staircase structure. Each tier comprises a conductive layer. The plurality of tiers includes at least a first tier and a second tier. The inductor has a first contact electrically coupling the first tier and the second tier. A first portion of a die is occupied by a memory sub-component comprising at least one three-dimensional (3D) NAND memory component and a second portion of the die is occupied by the inductor.
An apparatus comprising:
A method of forming an on-chip inductor, the method comprising:
An integrated circuit (IC)-based inductor comprising:
Dependencies are inferred from the claim text.