Memory control circuit and control method thereof

Abstract

A memory control circuit includes an access control circuit, a connection pad circuit, and a pad control circuit. The connection pad circuit includes a transceiver circuit and a receiver circuit. The transceiver circuit and the receiver circuit are connected to a memory through an external pad. The pad control circuit is connected between the access control circuit and the receiver circuit. The pad control circuit executes a read command, and receives data from the memory. The pad control circuit executes a write command or receives the data, the pad control circuit turns off the output of the receiver circuit. The access control circuit executes a power save command that the receiver circuit enters a power save mode. The pad control circuit decreases an operating current of the receiver circuit to minimum and forces an internal signal level of the receiver circuit. The receiver circuit enters a deep power save state.

Dependencies are inferred from the claim text.