Apparatuses and methods for faciliatating a dynamic clock frequency for at-speed testing

A device, comprising:

• a processing system including a processor;
• and
• a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations, the operations comprising:
• monitoring first data to identify a first plurality of test points;
• analyzing the first plurality of test points to identify the first data as being associated with a first time domain included in a plurality of time domains, wherein respective portions of a device under test (DUT) are operative in accordance with a given time domain included in the plurality of time domains;
• and
• based on the analyzing of the first plurality of test points, generating first control signals to cause a first clock signal to be adapted to generate a second clock signal that is different from the first clock signal.