Circuit and method for measuring capacitance and capacitance-voltage characteristics of microelectronic device

A circuit for measuring capacitance and capacitance-voltage characteristics of a microelectronic device, comprising a pulse generation sub-circuit, a sub-circuit P and a sub-circuit N, wherein

• the pulse generation sub-circuit is configured to generate clock pulses CLK1 and CLK2 with non-overlapping active levels;
• the sub-circuit P comprises a first current mirror, a first large capacitor, a first transmission gate, a second transmission gate, a first OR gate, a first AND gate, a first NOT gate, a second NOT gate, and a third NOT gate;
• a first output terminal of the first current mirror is connected to a first terminal of the first transmission gate, a second terminal of the first transmission gate is connected to a first terminal of the second transmission gate, and a second terminal of the second transmission gate is connected to a VBP;
• a second output terminal of the first current mirror is grounded through the first large capacitor;
• an input terminal of the first OR gate is connected to the clock pulse CLK1, a CTRP, and a VSS, an output terminal of the first OR gate is connected to a first control terminal of the first transmission gate, and the output terminal of the first OR gate is further connected to a second control terminal of the first transmission gate through the first NOT gate;
• an input terminal of the first AND gate is connected to a VDD, the CTRP passing through the second NOT gate, and the clock pulse CLK2, an output terminal of the first AND gate is connected to a first control terminal of the second transmission gate, and the output terminal of the first AND gate is further connected to a second control terminal of the second transmission gate through the third NOT gate;
• the sub-circuit N comprises a second current mirror, a second large capacitor, a third transmission gate, a fourth transmission gate, a second OR gate, a second AND gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, and a seventh NOT gate;
• a first output terminal of the second current mirror is connected to a first terminal of the third transmission gate, a second terminal of the third transmission gate is connected to a first terminal of the fourth transmission gate, and a second terminal of the fourth transmission gate is connected to a VBN;
• a second output terminal of the second current mirror is grounded through the second large capacitor;
• an input terminal of the second OR gate is connected to the clock pulse CLK1, a CTRN, and an LHN passing through the fourth NOT gate, an output terminal of the second OR gate is connected to a first control terminal of the third transmission gate, and the output terminal of the second OR gate is further connected to a second control terminal of the third transmission gate through the fifth NOT gate;
• an input terminal of the second AND gate is connected to the LHN, the CTRN passing through the sixth NOT gate, and the clock pulse CLK2, an output terminal of the second AND gate is connected to a first control terminal of the fourth transmission gate, and the output terminal of the second AND gate is further connected to a second control terminal of the fourth transmission gate through the seventh NOT gate;
• one terminal of a to-be-measured device capacitor is connected to a connection node between the first transmission gate and the second transmission gate, and the other terminal of the to-be-measured device capacitor is connected to a connection node between the third transmission gate and the fourth transmission gate;
• and
• high potential terminals of the first current mirror and the second current mirror are each connected to a VDA, substrates of all P-channel metal-oxide semiconductor (PMOS) transistors in the four transmission gates are each connected to a negative power supply VSB, substrates of all N-channel metal-oxide semiconductor (NMOS) transistors are each connected to a positive power supply VDD, positive power supplies of all gate circuits are each connected to the VDD, and low power supplies of all the gate circuits are each connected to the VSS, while low power supplies of the second OR gate, the second AND gate, the fourth NOT gate, the fifth NOT gate, and the seventh NOT gate are each connected to a VSA.