US 2025/0069564 A1Published application

Semiconductor device, display module, and electronic device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorAtsushi UMEZAKI

Life of this patent

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Abstract

A first flipflop outputs a first signal synchronized with a first clock signal. In the first transistor, the first clock signal is input to a first terminal and the second signal is output from a second terminal. In the fourth transistor, a first signal is input to a first terminal and a second terminal is electrically connected to a gate of the first transistor. In the sixth transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the fourth transistor, and the gate of the sixth transistor is electrically connected to the first terminal.

Claims6

Dependent claims

A display device comprising:

a gate driver circuit and a pixel,
wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a first gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to the first gate signal line,
wherein the other of the source and the drain of the second transistor is electrically connected to a power supply line,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the power supply line,
wherein a gate of the third transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a second gate signal line,
wherein a gate of the fourth transistor is electrically connected to the second gate signal line, wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a third gate signal line,
wherein a gate of the fifth transistor is electrically connected to the third gate signal line,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the power supply line,
wherein a gate of the seventh transistor is electrically connected to the gate of the first transistor,
wherein, when the other of the source and the drain of the sixth transistor is in a conduction state with the gate of the second transistor and the gate of the third transistor through at least a channel formation region of the sixth transistor, a potential to turn on the second transistor and the third transistor is input to the gate of the second transistor and the gate of the third transistor,
wherein a channel width to a channel length of the fourth transistor is 0.9 to 1.1 times than a channel width to a channel length of the fifth transistor,
wherein the pixel includes an eighth transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to a pixel electrode,
wherein the other of the source and the drain of the eighth transistor is electrically connected to a source signal line, and
wherein a gate of the eighth transistor is electrically connected to the first gate signal line.

22 more elements

A display device comprising:

a gate driver circuit and a pixel,
wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a first gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to the first gate signal line,
wherein the other of the source and the drain of the second transistor is electrically connected to a power supply line,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the power supply line,
wherein a gate of the third transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a second gate signal line,
wherein a gate of the fourth transistor is electrically connected to the second gate signal line,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a third gate signal line,
wherein a gate of the fifth transistor is electrically connected to the third gate signal line,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the power supply line,
wherein a gate of the seventh transistor is electrically connected to the gate of the first transistor,
wherein, when the other of the source and the drain of the sixth transistor is in a conduction state with the gate of the second transistor and the gate of the third transistor through at least a channel formation region of the sixth transistor, a potential to turn on the second transistor and the third transistor is input to the gate of the second transistor and the gate of the third transistor,
wherein a channel width to a channel length of the fourth transistor is 0.9 to 1.1 times than a channel width to a channel length of the fifth transistor,
wherein a channel width to a channel length of the first transistor is larger than a channel width to a channel length of the second transistor,
wherein the channel width to the channel length of the first transistor is larger than a channel width to a channel length of the third transistor,
wherein the channel width to the channel length of the first transistor is larger than the channel width to the channel length of the fourth transistor,
wherein the channel width to the channel length of the first transistor is larger than the channel width to the channel length of the fifth transistor,
wherein the pixel includes an eighth transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to a pixel electrode,
wherein the other of the source and the drain of the eighth transistor is electrically connected to a source signal line, and
wherein a gate of the eighth transistor is electrically connected to the first gate signal line.

27 more elements

A display device comprising:

a gate driver circuit and a pixel,
wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a first gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to the first gate signal line,
wherein the other of the source and the drain of the second transistor is electrically connected to a power supply line,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the power supply line,
wherein a gate of the third transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a second gate signal line,
wherein a gate of the fourth transistor is electrically connected to the second gate signal line,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a third gate signal line,
wherein a gate of the fifth transistor is electrically connected to the third gate signal line,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the power supply line,
wherein a gate of the seventh transistor is electrically connected to the gate of the first transistor,
wherein, when the other of the source and the drain of the sixth transistor is in a conduction state with the gate of the second transistor and the gate of the third transistor through at least a channel formation region of the sixth transistor, a potential to turn on the second transistor and the third transistor is input to the gate of the second transistor and the gate of the third transistor,
wherein a channel width to a channel length of the fourth transistor is 0.9 to 1.1 times than a channel width to a channel length of the fifth transistor,
wherein a first conductive layer is configured to be the other of the source and the drain of the first transistor, a second conductive layer is configured to be the gate of the first transistor, and a third conductive layer is configured to be the one of the source and the drain of the first transistor,
wherein an area of the first conductive layer overlapping the second conductive layer is larger than an area of the third conductive layer overlapping the second conductive layer,
wherein the pixel includes an eighth transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to a pixel electrode,
wherein the other of the source and the drain of the eighth transistor is electrically connected to a source signal line, and
wherein a gate of the eighth transistor is electrically connected to the first gate signal line.

25 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/944,525Filed 12 Nov 2024
Priority: JP 2014-09031424 Apr 2014
Published: 27 Feb 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G09G 3/3674
Control of matrices with row and column drivers: details of drivers for scan electrodes
G09G 3/20
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes: for presentation of an…
G09G 3/3688
Details of drivers for data electrodes: suitable for active matrices only
G11C 19/28
Digital stores in which the information is moved stepwise, e.g. shift registers: using semiconductor elements

Family

Application14/680,520Division · filed 7 Apr 2015
Application16/263,153Continuation · filed 31 Jan 2019
Application17/029,099Continuation · filed 23 Sep 2020
Application18/083,282Continuation · filed 16 Dec 2022
Application18/944,525Continuation
Application16/263,153Division
US 10,199,006 B2Related patent
US 10,839,766 B2Related patent
US 12,190,842 B2Related patent
US 2015/0310929 A1Published application
US 2019/0164517 A1Published application
US 2021/0005156 A1Published application
US 2023/0162697 A1Published application
US 2025/0069564 A1This patent

From the US filing history. Foreign family members aren’t listed.

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Citations

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Abstract

A display device comprising:

a gate driver circuit and a pixel,
wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a first gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to the first gate signal line,
wherein the other of the source and the drain of the second transistor is electrically connected to a power supply line,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the power supply line,
wherein a gate of the third transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a second gate signal line,
wherein a gate of the fourth transistor is electrically connected to the second gate signal line, wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a third gate signal line,
wherein a gate of the fifth transistor is electrically connected to the third gate signal line,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the power supply line,
wherein a gate of the seventh transistor is electrically connected to the gate of the first transistor,
wherein, when the other of the source and the drain of the sixth transistor is in a conduction state with the gate of the second transistor and the gate of the third transistor through at least a channel formation region of the sixth transistor, a potential to turn on the second transistor and the third transistor is input to the gate of the second transistor and the gate of the third transistor,
wherein a channel width to a channel length of the fourth transistor is 0.9 to 1.1 times than a channel width to a channel length of the fifth transistor,
wherein the pixel includes an eighth transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to a pixel electrode,
wherein the other of the source and the drain of the eighth transistor is electrically connected to a source signal line, and
wherein a gate of the eighth transistor is electrically connected to the first gate signal line.

22 more elements

Facts

Application

18/944,525Filed 12 Nov 2024

Priority

JP 2014-09031424 Apr 2014

Published

27 Feb 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification15 codes

G09G 3/3674
Control of matrices with row and column drivers: details of drivers for scan electrodes
G09G 3/20
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes: for presentation of an…
G09G 3/3688
Details of drivers for data electrodes: suitable for active matrices only
G11C 19/28
Digital stores in which the information is moved stepwise, e.g. shift registers: using semiconductor elements

Family

Application14/680,520Division · filed 7 Apr 2015

Application16/263,153Continuation · filed 31 Jan 2019

Application17/029,099Continuation · filed 23 Sep 2020

Application18/083,282Continuation · filed 16 Dec 2022

Application18/944,525Continuation

Application16/263,153Division

US 10,199,006 B2Related patent

US 10,839,766 B2Related patent

US 12,190,842 B2Related patent

US 2015/0310929 A1Published application

US 2019/0164517 A1Published application

US 2021/0005156 A1Published application

US 2023/0162697 A1Published application

US 2025/0069564 A1This patent

From the US filing history. Foreign family members aren’t listed.