Vertical memory device and method of manufacturing the same

A vertical memory device comprising:

• a substrate;
• a plurality of electrode structures extending in a vertical direction on the substrate and constituting a plurality of lines in a first horizontal direction;
• a plurality of partition pillars extending on the substrate in the vertical direction and contacting at least one of the plurality of electrode structures;
• a word line cut disposed apart from the plurality of electrode structures in a horizontal direction and extending in the vertical direction;
• and
• a gate stack structure comprising gate electrodes and interlayer insulating layers alternately stacked on the substrate along a sidewall of each of the plurality of electrode structures and the word line cut, wherein the gate electrodes are electrically connected to the plurality of electrode structures,
• wherein, in a plan view, the word line cut is wavy-shaped, and
• wherein each of the plurality of electrode structures comprises:
• a vertical electrode extending in the vertical direction on the substrate;
• and
• a switching material layer surrounding the vertical electrode and extending in the vertical direction.

A vertical memory device comprising:

• a substrate;
• a plurality of electrode structures extending in a vertical direction on the substrate and constituting a plurality of lines in a first horizontal direction;
• a plurality of partition pillars each extending on the substrate in the vertical direction and contacting at least one of the plurality of electrode structures;
• a plurality of trim patterns contacting the plurality of electrode structures or the plurality of partition pillars and extending in the vertical direction on the substrate;
• a word line cut disposed apart from each of the plurality of electrode structures, the plurality of partition pillars, and the plurality of trim patterns in a horizontal direction and extending in the vertical direction;
• and
• a gate stack structure comprising gate electrodes and interlayer insulating layers alternately stacked on the substrate along a sidewall of each of the plurality of electrode structures, the plurality of partition pillars, and the word line cut, wherein the gate electrodes are electrically connected to the plurality of electrode structures,
• wherein, in a plan view, each of the plurality of trim patterns and the word line cut are wavy shaped,
• wherein the plurality of electrode structures and the plurality of partition pillars form a plurality of sub channels extending in the first horizontal direction,
• wherein the plurality of trim patterns form a connection channel connecting the plurality of sub channels that are apart from each other in a second horizontal direction, and
• wherein each of the plurality of electrode structures comprises:
• a vertical electrode extending in the vertical direction on the substrate;
• and
• a switching material layer surrounding the vertical electrode and extending in the vertical direction.