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US 2025/0063793 A1Published application
Method of manufacturing semiconductor device and associated memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsNUO XU, ZHIQIANG WU
Life of this patent
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Abstract
A semiconductor device includes a substrate including a planar portion and a mesa portion over the planar portion; an oxide layer over the mesa portion; a ferroelectric material strip covering a protruding plane of the oxide layer and exposing a side plane of the oxide layer; and a gate strip over the ferroelectric material strip and overlapping the oxide layer.
Claims20
A semiconductor device, comprising:
- a substrate including a planar portion and a mesa portion over the planar portion;
- an oxide layer over the mesa portion;
- a ferroelectric material strip covering a protruding plane of the oxide layer and exposing a side plane of the oxide layer;
- and
- a gate strip over the ferroelectric material strip and overlapping the oxide layer.
2 more elements
A semiconductor device, comprising:
- a plurality of gate electrode layers and a plurality of insulating layers alternatingly disposed with the plurality of gate electrode layers over a substrate, the plurality of gate electrode layers and the plurality of insulating layers including a ring shape having a first sidewall and a second sidewall;
- a ferroelectric material layer disposed on the first sidewall;
- an oxide layer disposed on the ferroelectric material layer and the second sidewall;
- and
- a channel layer laterally surrounded by the plurality of gate electrode layers and the plurality of insulating layers, and adjacent to the oxide layer.
2 more elements
A method of forming a memory device, comprising:
- forming a plurality of memory cells connected together, each of the plurality of memory cells including a first transistor, a second transistor and a capacitor, wherein the first transistor and the second transistor share a gate terminal, a source terminal and a drain terminal;
- electrically connecting the capacitor to the gate terminal;
- and
- forming a selection transistor to connect to the plurality of memory cells.
1 more element
Dependencies are inferred from the claim text.