Contact gate isolation

A method comprising:

• forming a channel layer over a substrate;
• forming a gate structure over the channel layer by:
• forming gate spacers,
• forming a gate dielectric layer over the channel layer, wherein the gate dielectric layer is disposed along sidewalls of gate spacers, and
• forming a gate electrode layer over the gate dielectric layer;
• recessing the gate dielectric layer to expose sidewalls of the gate electrode layer;
• and
• forming a lining layer to cover the exposed sidewalls of the gate electrode layer.

A transistor comprising:

• a semiconductor layer disposed between a first epitaxial source/drain and a second epitaxial source/drain;
• a gate structure disposed over the semiconductor layer, wherein the gate structure includes a gate stack and gate spacers disposed along sidewalls of the gate stack, wherein:
• the gate stack includes a gate electrode disposed over a high-k gate dielectric, wherein the high-k gate dielectric is disposed along lower portions of sidewalls of the gate electrode and the high-k gate dielectric is disposed between
• the gate spacers and the lower portions of the sidewalls of the gate electrode;
• and
• a gate isolation liner disposed along upper portions of sidewalls of the gate electrode, wherein the gate isolation liner is disposed over the gate spacers and the high-k gate dielectric.