Semiconductor device structure and methods of forming the same

A method, comprising:

• a first etch process performed on a gate electrode, wherein the first etch process includes a plasma etch process with:
• a first source power with an 80% duty cycle at a power level ranging from about 1500 W to about 2500 W;
• and
• a first bias power with a 30% duty cycle at a voltage level ranging from about 150 V to about 250 V and 50% duty cycle at a voltage level ranging from about 5 V to about 100 V immediately following the 30% duty cycle;
• and
• a second etch process performed on a mask structure disposed on the gate electrode, wherein the second etch process includes a plasma etch process with:
• a second source power with a 100% duty cycle at a power level ranging from about 10 W to about 200 W;
• and
• a second bias power with a 50% duty cycle at a voltage level ranging from about 200 V to about 800 V.

A method, comprising:

• forming a plurality of fins from a semiconductor substrate;
• forming isolation regions around each fin of the plurality of fins;
• depositing a gate electrode over the plurality of fins;
• forming a mask structure over the gate electrode;
• forming an opening in the mask structure;
• extending the opening through the gate electrode by a first plasma etch process with a first bias power having a frequency to control a lateral etch of the gate electrode;
• extending the opening through the isolation region;
• etching a sidewall of the mask structure within the opening by a second plasma etch process with a second bias power having a frequency to control a vertical etch of the mask structure and to remove a sharp corner in the sidewall of the mask structure exposed to the opening;
• and
• filling the opening with a dielectric layer.