Semiconductor memory device and method of manufacturing the same

A semiconductor memory device comprising:

• a plurality of bit lines extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction;
• a plurality of active portions, at least two of the plurality of active portions being on the plurality of bit lines, respectively;
• a pad insulating layer on the plurality of active portions and comprising a plurality of pad through holes corresponding to the plurality of active portions;
• a plurality of landing pads in the plurality of pad through holes and electrically connected to the plurality of active portions, respectively, and comprising a plurality of protrusions protruding towards an upper portion of the pad insulating layer;
• a lower conductive layer bordering side surfaces of the plurality of protrusions of the plurality of landing pads;
• a plurality of lower electrodes on the plurality of landing pads, respectively, and electrically connected to the plurality of landing pads;
• a ferroelectric layer bordering the plurality of lower electrodes and being on the lower conductive layer;
• an upper electrode bordering the ferroelectric layer;
• an electrode insulating layer on the upper electrode;
• and
• a plate line on the electrode insulating layer and the upper electrode and electrically connected to the upper electrode,
• wherein the plate line is electrically connected to the lower conductive layer through a through via, and
• wherein the lower conductive layer, the through via, and the plate line electrically connect the lower electrode to the upper electrode when the active portion is in an off-state.

A semiconductor memory device comprising:

• a plurality of bit lines extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction;
• a plurality of word lines extending in the second direction and spaced apart from each other in the first direction;
• a plurality of active portions, at least two of the plurality of active portions being on the plurality of bit lines, respectively;
• a plurality of gate insulating layers on both sides of the plurality of active portions, respectively;
• a pad insulating layer on the plurality of active portions and comprising a plurality of pad through holes corresponding to the plurality of active portions;
• a plurality of landing pads in the plurality of pad through holes and electrically connected to the plurality of active portions, respectively, and comprising a plurality of protrusions protruding towards an upper portion of the pad insulating layer;
• a lower conductive layer bordering side surfaces of the plurality of protrusions of the plurality of landing pads;
• a plurality of lower electrodes on the plurality of landing pads, respectively, and electrically connected to the plurality of landing pads;
• a ferroelectric layer bordering the plurality of lower electrodes and being on the lower conductive layer;
• an upper electrode bordering the ferroelectric layer;
• an electrode insulating layer on the upper electrode;
• and
• a plate line on the electrode insulating layer and the upper electrode and electrically connected to the upper electrode,
• wherein the plurality of word lines are spaced apart from the plurality of active portions with the plurality of gate insulating layers therebetween,
• wherein a width of the plurality of protrusions in the first direction is greater than a width of a portion of the plurality of landing pads in the first direction that is located in the plurality of pad through holes, and
• wherein the plate line is electrically connected to the lower conductive layer through a through via with a greater width in the first direction than the lower conductive layer.